Transforming Reconfigurable Systems by Luk Wayne & Constantinides George A

Author:Luk Wayne & Constantinides George A
Language: eng
Format: epub
ISBN: 9781783266982
Publisher: Imperial College Press
Published: 2015-02-25T16:00:00+00:00

Fig. 7.7. An implementation of the Nengo digit-recognition model on a DE4 FPGA board with touch-screen.

7.5. Conclusion

We have demonstrated that a quad-core BlueVec (NIOS II + vector) machine has performance that falls within a factor of two of the custom pipeline for our neural computation case study, and has similar logic usage. The Bluespec code for BlueVec together with vectorised C code proved to be much more compact and easy to develop than the custom pipeline despite using a high-level language (Bluespec).

Vector processing also allows the memory bottleneck to be managed through efficient use of burst access to DDR2/DDR3 memory. Given that the memory bandwidth can easily become the bottleneck, inefficiency in the compute vector compute structures on FPGA becomes mostly irrelevant. Perhaps it is not too surprising that a vector multiprocessor can achieve excellent performance on FPGA given that GPUs (which are also vector multiprocessors) are highly competitive [Ref. 17]. FPGAs do, however, offer the flexibility to tailor the vector unit to the application, e.g. using custom arithmetic operations. But perhaps more importantly for massively parallel systems, FPGAs offer the ability to customise the inter-chip communication network to suit the application.

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